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ADVANCE CY14E108L, CY14E108N
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features

Functional Description
The Cypress CY14E108L/CY14E108N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 1024K words of 8 bits each or 512K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
20 ns, 25 ns, and 45 ns access times Internally organized as 1024K x 8 (CY14E108L) or 512K x 16 (CY14E108N) Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrap(R) nonvolatile elements initiated by software, device pin, or AutoStore(R) on power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 5V +10% operation Commercial and industrial temperatures 48-pin FBGA, 44 and 54-pin TSOP II packages Pb-free and RoHS compliance
Logic Block Diagram
VCC
VCAP
Address A0 - A19
CE OE WE
[1]
[1]
DQ0 - DQ7 CY14E108L CY14E108N HSB
BHE BLE
VSS
Note 1. Address A0 - A19 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A18 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation Document Number: 001-45524 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 24, 2008
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ADVANCE CY14E108L, CY14E108N
Pinouts
Figure 1. Pin Diagram - 48 FBGA (x8) Top View (not to scale)
1 NC NC DQ0 VSS VCC DQ3 2 OE NC NC DQ1 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC DQ5 DQ6 NC WE A11 6 NC NC DQ4 VCC VSS DQ7 NC A19 A B C D E F G H
48-FBGA
(x16) Top View (not to scale)
1 BLE 2 OE 3 A0 A3 A5 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE 6 NC DQ0 A B C D E F G H
48-FBGA
DQ8 BHE DQ9 DQ10 VSS
DQ1 DQ2 DQ3 DQ4 VCC VSS
DQ11 A17
DQ2 VCAP NC A14 A12 A9
VCC DQ12 VCAP DQ14 DQ13 DQ15 HSB
A18
A14 A12 A9
DQ5 DQ6 WE A11 DQ7
[2] NC
[2] HSB NC
A18
A8
A8
Figure 2. Pin Diagram - 44/54 TSOP II
NC [2] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC A19 A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
NC [2] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB A18 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC
44 - TSOP II
(x8)
54 - TSOP II
(x16)
Top View (not to scale)
Top View (not to scale)
Note 2. Address expansion for 16 Mbit. NC pin not connected to die.
Document Number: 001-45524 Rev. *A
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ADVANCE CY14E108L, CY14E108N
Pin Definitions
Pin Name A0 - A19 A0 - A18 DQ0 - DQ7
DQ0 - DQ15
IO Type Input
Description Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on operation. Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on operation. Input Input Input Input Input Ground Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. IO pins are tri-stated on deasserting OE high. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Ground for the Device. Must be connected to the ground of the system.
WE CE OE BHE BLE VSS VCC HSB
Power Supply Power Supply Inputs to the Device. Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM to nonvolatile elements. No Connect No Connect. Do not connect this pin to the die.
VCAP NC
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ADVANCE CY14E108L, CY14E108N
Device Operation
The CY14E108L/CY14E108N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14E108L/CY14E108N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations.
To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress. Figure 3. AutoStore Mode
Vcc
0.1uF 10kOhm Vcc
SRAM Read
The CY14E108L/CY14E108N performs a READ cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-19 or A0-18 determines which of the 1,048,576 data bytes or 524,288 words of 16 bits each is accessed. When the read is initiated by an address transition, the outputs are valid after a delay of tAA. If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later. The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
WE
V CAP
V SS
V CAP
Hardware STORE Operation
The CY14B108L/CY14B108N provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B108L/CY14B108N conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14B108L/CY14B108N continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it is allowed a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW is inhibited until HSB returns HIGH. During any STORE operation, regardless of how it was initiated, the CY14B108L/CY14B108N continues to drive the HSB pin LOW, releasing it only when the STORE is complete.Upon completion of the STORE operation, the CY14B108L/CY14B108N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
SRAM Write
A WRITE cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common IO pins DQ0-15 are written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of a CE controlled WRITE. It is recommended that OE be kept HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B108L/CY14B108N stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB; Software Store activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108L/CY14B108N. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the section DC Electrical Characteristics on page 7 for the size of VCAP.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
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ADVANCE CY14E108L, CY14E108N
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B108L/CY14B108N software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If there are intervening READ or WRITE accesses, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle The software sequence may be clocked with CE controlled READs or OE controlled READs. After the sixth address in the sequence is entered, the STORE cycle commences and the chip Table 1. Mode Selection CE H L L L WE X H L H OE X L X L
is disabled. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.
A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable
IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data
Power Standby Active Active Active[3,4,5]
L
H
L
Active[3,4,5]
Notes 3. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 4. While there are 20/19 address lines on the CY14B108L/CY14B108N, only the lower 16 lines are used to control software modes. 5. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
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ADVANCE CY14E108L, CY14E108N
Table 1. Mode Selection (continued) CE L WE H OE L A15 - A0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall IO Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active ICC2[3,4,5]
L
H
L
Active[3,4,5]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14E108L/CY14E108N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14E108L/CY14E108N is in a write mode (both CE and WE LOW) at power up, after a RECALL or STORE, the write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY Application Note AN1064.
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ADVANCE CY14E108L, CY14E108N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +150C Supply Voltage on VCC Relative to GND ..........-0.5V to 7.0V Voltage Applied to Outputs in High-Z State....................................... -0.5V to VCC + 0.5V Input Voltage.............................................-0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current [6] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 4.5V to 5.5V 4.5V to 5.5V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)[8] Parameter ICC1 Description Average VCC Current Test Conditions tRC = 20 ns tRC = 25 ns tRC = 45 ns Dependent on output loading and cycle rate.Values obtained without output loads. IOUT = 0 mA All Inputs Don't Care, VCC = Max Average current for duration tSTORE Commercial Min Max 70 70 55 75 75 57 12 38 Unit mA mA mA mA mA mA mA mA
Industrial
ICC2 ICC3[7]
Average VCC Current During STORE
Average VCC Current at WE > (VCC - 0.2). All other I/P cycling. tRC= 200 ns, 5V, 25C Dependent on output loading and cycle rate. Values obtained typical without output loads. Average VCAP Current All Inputs Don't Care, VCC = Max During AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. -2 -200 -2 2.0 Vss - 0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V Rated 122 2.4
ICC4 ISB
12 6
mA mA
IIX
Input Leakage Current VCC = Max, VSS < VIN < VCC (except HSB) Input Leakage Current VCC = Max, VSS < VIN < VCC (For HSB)
+2 +2 +2 VCC + 0.5 0.8 0.4 164
A A A V V V V F
IOZ VIH VIL VOH VOL VCAP
Off-State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
VCC = Max, VSS < VIN < VCC, CE or OE > VIH
Notes 6. Outputs shorted for no more than one second. No more than one output shorted at a time. 7. Typical conditions for the active current shown on the front page of the data sheet are average values at 25C (room temperature) and VCC = 5V. Not 100% tested. 8. The HSB pin has IOUT=-10uA for VOH of 2.4V. This parameter is characterized but not tested.
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ADVANCE CY14E108L, CY14E108N
Capacitance
In the following table, the capacitance parameters are listed [9]. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max 14 14 Unit pF pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed [9]. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-FBGA 44-TSOP II 54-TSOP II 28.82 7.84 31.11 5.56 30.73 6.08 Unit C/W C/W
JA JC
Figure 4. AC Test Loads
963 5.0V OUTPUT 30 pF R2 512 R1
963 5.0V OUTPUT 5 pF R1
for tri-state specs
R2 512
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <5 ns Input and Output Timing Reference Levels .................... 1.5V
Note 9. These parameters are guaranteed but not tested.
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ADVANCE CY14E108L, CY14E108N
AC Switching Characteristics
In the following table, the AC switching characteristics are listed. Parameters Cypress Parameters tACE tRC[10] tAA[11] tDOE tOHA tLZCE[12] tHZCE[12] tLZOE[12] tHZOE[12] tPU[10] tPD[10] tDBE tLZBE tHZBE tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE[12,13] tLZWE[12] tBW Alt Parameters tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Description 20 ns Min Max 25 ns Min Max 45 ns Min Max Unit
SRAM Read Cycle Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write 3 15 20 15 15 8 0 15 0 0 8 3 20 0 8 25 20 20 10 0 20 0 0 10 3 30 0 20 10 0 10 45 30 30 15 0 30 0 0 15 0 8 0 25 12 0 15 3 3 8 0 10 0 45 20 20 20 10 3 3 10 0 15 20 25 25 12 3 3 15 25 45 45 20 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SRAM Write Cycle
Notes 10. WE must be HIGH during SRAM read cycles. 11. Device is continuously selected with CE and OE both LOW. 12. Measured 200 mV from steady state output voltage. 13. If WE is LOW when CE goes LOW, the output goes into high impedance state.
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ADVANCE CY14E108L, CY14E108N
AutoStore and Power Up RECALL
Parameters tHRECALL [14] tSTORE [15] VSWITCH tVCCRISE Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 CY14E108L/CY14E108N Min Max 20 15 4.4 Unit ms ms V s
Software Controlled STORE and RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[16, 17] Parameters tRC tAS tCW tGHAX tRECALL tSS [18, 19] Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 20ns Min 20 0 15 1 200 70 Max 25 0 20 1 200 70 25ns Min Max 45 0 30 1 200 70 45ns Min Max Unit ns ns ns ns s s
Hardware STORE Cycle
Parameters tDELAY [20] tHLHX Description Time allowed to complete SRAM cycle Hardware STORE pulse width CY14E108L/CY14E108N Min 1 15 Max 70 Unit s ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 21]
tRC
ADDRESS
t AA t OHA
DQ (DATA OUT) DATA VALID
Notes 14. tHRECALL starts from the time VCC rises above VSWITCH. 15. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place. 16. The software sequence is clocked with CE controlled or OE controlled reads. 17. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles. 18. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command. 19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command 20. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete. 21. HSB must remain HIGH during READ and WRITE cycles.
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ADVANCE CY14E108L, CY14E108N
Switching Waveforms (continued)
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[10, 21, 23]
tRC
ADDRESS
CE
tLZCE
tACE
tPD tHZCE
OE
tLZOE
BHE , BLE
tDOE
t HZOE
DQ (DATA OUT)
tLZBE t PU
tDBE
DATA VALID
tHZCE tHZBE
ACTIVE
ICC
STANDBY
Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23]
t WC
ADDRESS
t SCE
CE
t HA
t AW t SA
WE
t PWE
BHE , BLE
t BW t SD t HD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
t LZWE
Notes 22. CE or WE must be >VIH during address transitions. 23. BHE and BLE are applicable for x16 configuration only.
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ADVANCE CY14E108L, CY14E108N
Switching Waveforms (continued)
Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23]
tWC
ADDRESS
tSA
CE
tSCE tAW tHA tPWE
WE
BHE , BLE
tBW
tSD tHD
DATA VALID
DATA IN
DATA OUT
HIGH IMPEDANCE
Figure 9. AutoStore or Power Up RECALL[24]
VCC VSWITCH
STORE occurs only if a SRAM write has happened
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
Note 24. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
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ADVANCE CY14E108L, CY14E108N
Switching Waveforms (continued)
Figure 10. CE Controlled Software STORE/RECALL Cycle[17]
Figure 11. OE Controlled Software STORE/RECALL Cycle[17]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tAS
OE
tCW tGHAX
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
DQ (DATA)
DATA VALID
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ADVANCE CY14E108L, CY14E108N
Switching Waveforms (continued)
Figure 12. Hardware STORE Cycle[20]
Figure 13. Soft Sequence Processing[18, 19]
tSS
tSS
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ADVANCE CY14E108L, CY14E108N
Ordering Information
Speed (ns) 20 Ordering Code CY14E108L-ZS20XCT CY14E108L-ZS20XIT CY14E108L-ZS20XI CY14E108L-BA20XCT CY14E108L-BA20XIT CY14E108L-BA20XI CY14E108L-ZSP20XCT CY14E108L-ZSP20XIT CY14E108L-ZSP20XI CY14E108N-BA20XCT CY14E108N-BA20XIT CY14E108N-BA20XI CY14E108N-ZSP20XCT CY14E108N-ZSP20XIT CY14E108N-ZSP20XI 25 CY14E108L-ZS25XCT CY14E108L-ZS25XIT CY14E108L-ZS25XI CY14E108L-BA25XIT CY14E108L-BA25XI CY14E108N-BA25XCT CY14E108L-ZSP25XCT CY14E108L-ZSP25XIT CY14E108L-ZSP25XI CY14E108N-BA25XCT CY14E108N-BA25XIT CY14E108N-BA25XI CY14E108N-ZSP25XCT CY14E108N-ZSP25XIT CY14E108N-ZSP25XI Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Commercial Industrial Commercial Industrial Commercial Commercial Industrial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
Document Number: 001-45524 Rev. *A
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ADVANCE CY14E108L, CY14E108N
Ordering Information (continued)
Speed (ns) 45 Ordering Code CY14E108L-ZS45XCT CY14E108L-ZS45XIT CY14E108L-ZS45XI CY14E108L-BA45XCT CY14E108L-BA45XIT CY14E108L-BA45XI CY14E108L-ZSP45XCT CY14E108L-ZSP45XIT CY14E108L-ZSP45XI CY14E108N-BA45XCT CY14E108N-BA45XIT CY14E108N-BA45XI CY14E108N-ZSP45XCT CY14E108N-ZSP45XIT CY14E108N-ZSP45XI Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts.
Part Numbering Nomenclature
CY 14 E 108 L - ZS P 20 X C T Option: T - Tape & Reel Blank - Std. Pb-Free Package: BA - 48 FBGA ZS - TSOP II
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
P - 54 Pin Blank - 44 Pin
Speed: 20 - 20ns 25 - 25 ns 45 - 45 ns
Data Bus: L - x8 N - x16
Voltage: E - 5.0V
Density: 108 - 8 Mb
NVSRAM 14 - Auto Store + Software Store + Hardware Store
Cypress
Document Number: 001-45524 Rev. *A
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ADVANCE CY14E108L, CY14E108N
Package Diagrams
Figure 14. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
Document Number: 001-45524 Rev. *A
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ADVANCE CY14E108L, CY14E108N
Package Diagrams
(continued) Figure 15. 48-ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 10.000.10 10.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75
0.530.05
0.25 C
B 0.210.05 0.15 C 0.15(4X)
6.000.10
SEATING PLANE 0.36 C 1.20 MAX
51-85128-*D
Document Number: 001-45524 Rev. *A
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ADVANCE CY14E108L, CY14E108N
Package Diagrams
(continued) Figure 16. 54-Pin TSOP II (51-85160)
51-85160-**
Document Number: 001-45524 Rev. *A
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ADVANCE CY14E108L, CY14E108N
Document History Page
Document Title: CY14E108L/CY14E108N 8 Mbit (1024K x 8/512K x 16) nvSRAM Document Number: 001- 45524 REV. ** ** ECN NO. 2428826 2520023 Submission Date See ECN 06/23/08 Orig. of Change GVCH GVCH/PYRS New Data Sheet Updated ICC1 for tRC=20ns, 25ns and 45ns access speed for both industrial and Commecial temperature Grade Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II packages Changed tCW value from 16ns to 15ns Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
(c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-45524 Rev. *A
Revised June 24, 2008
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AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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